The present invention relates to a semiconductor device and a power converter using the same, particularly a planar type semiconductor device having a high blocking voltage not lower than 1.7 kV, as well as a power converter capable of handling a high voltage using such planar type semiconductor device.
Recently, improvements in blocking voltages of a planar type semiconductor devices has been remarkable. The term "planar type semiconductor device" refers to a semiconductor device wherein at least one pn junction is exposed to a main surface. In the planar type semiconductor device, as compared with the conventional mesa type and bevel type semiconductor devices, a high voltage blocking characteristic is obtained by only the diffusion of impurity from the main surface or the formation of an insulating film. Therefore, it is possible to share a fine patterning process with an IC or an LSI. Fine patterning is essential for the improvement of performance even in the case of a high voltage semiconductor device, and the development of planar type semiconductor devices using a fine patterning process is remarkable.
FIG. 3 is a plan view of a diode as an example of a planar type semiconductor device. In the semiconductor device, indicated at 1, there are formed a main electrode 22, field plate electrodes 221, 222, 223, 224 and 225 which surround the main electrode 22 in the form of tracks, and an electrode 23 whose potential is fixed to the potential of an n+ layer 14 (the mark "n+" is not shown in FIG. 3) as an outermost peripheral portion of the semiconductor device 1.
FIG. 4 is a sectional view taken on line A--A' of the semiconductor device of FIG. 3. In the semiconductor device 1, for example, an n- layer 12 is formed on a semiconductor substrate 11, and p layers 13, 131, 132, 133, 134 and 135 are diffused from an upper main surface, with n+ layer 14 being formed as an outermost peripheral layer. At a lower main surface, a main electrode 21 is in ohmic-contact with the semiconductor substrate 11. On the p layer 13 is formed the other electrode 22, a part of which extends onto the n- layer 12 through an insulating film 30. This portion is called a field plate which functions to relax an electric field induced upon reverse bias of both p layer 13 and n- layer 12. Particularly, this portion is effective in field relaxation of a corner region of the p layer 13 where the electric field is apt to become strong. The other p layers 131, 132, 133, 134 and 135 function to disperse applied voltages when a plus (i.e., positive) voltage is applied to one main electrode 21 and a minus (i.e., negative) voltage is applied to the other main electrode 22. The potential of the main electrode 21 is transmitted to the semiconductor substrate 11. Since the junction of the semiconductor substrate 11 and the n- layer 12 is n+/n- junction, both become almost equal in potential, and the n+ layer 14 also comes to have the same potential. Consequently, the p layer 13 and the n+ layer 14 assume the state of reverse bias, so that the p layers 131, 132, 133, 134 and 135 have an intermediate potential. For example, when 2,000 V is applied to one main electrode 21 and 0 V to the other main electrode 22, the potentials of the p layers 131, 132, 133, 134, 135 and n+ layer 14 are 300 V, 600 V, 900 V, 1,200 V, 1,500 V and about 2,000 V, respectively. By so dispersing the potentials it becomes possible to make the blocking voltage of the planar type semiconductor device 1 high.
Further, auxiliary electrodes 221, 222, 223, 224 and 225 are formed on the p layers 131, 132, 133, 134 and 135, respectively, each being provided with a field plate which has a length R extending on the n- layer 12. These field plates Rs also function to relax the electric field applied to the corner portions of the p layers. The n+ layer 14 is formed with a separate auxiliary electrode 23 and with a field plate extending inside the semiconductor device 1, which also functions to relax the electric field applied to the corner portion of the n+ layer 14. Thus, by both potential dispersion attained by the p layers 131, 132, 133, 134 and 135, and field relaxation attained by the field plates, it is possible to make the blocking voltage of the planar type semiconductor device high.
The p layers 131, 132, 133, 134 and 135 are each called an FLR (Field Limiting Ring). Further, the field plates extending on the n- layer toward the peripheral portion of the semiconductor device 1 are here designated as forward field plates (forward FPs), while the field plates extending toward the inside are here designated as reverse field plates (reverse FPs). Each voltage blocking region having FLR and FP is designated a termination region.
However, in the case where a planar type semiconductor device of a high blocking voltage having such FLRs and field plates are used in an inverter in a train such as, for example, a subway or a suburban train where the working environment is severe, the inverter undergoes great changes in humidity and temperature as compared with inverters used indoors. Consequently, there arise such problems as a decrease of blocking voltage and an increase of leakage current. Particularly, in an inverter train, the line voltage reaches 1,500 V, so even in the case of a three-level inverter having a neutral point voltage, a blocking voltage of 1,700 V or higher is required for the semiconductor device used therein. For implementing this requirement in terms of a planar structure, about eight or more FLRs are needed. The length of the termination region sometimes reaches 1,000 microns. Therefore, in the case of a package molded with an organic resin such as a module for example, it is easily influenced by variations in electric charge and water content in the resin, caused by changes in humidity and temperature. This results in deterioration in the voltage controlling ability of the inverter, and in the worst case, the operation of a train or the like may be impeded.
FIG. 5 is a partially enlarged view of FIG. 4 for explaining why there occur such inconveniences. In FIG. 5, the broken lines represent equipotential lines 40. It is seen that by the forward field plate R the equipotential lines 40 are extended in the peripheral direction and that the electric field of the n- layer 12 at the corner region of the p layer 134 is relaxed. As a result of an experiment conducted by the present inventors it turned out that in a high humidity condition there is generated a minus electric charge on the surface of the insulating film 30 of the semiconductor device 1, causing p inversion of the surface of the n- layer 12. Examples of such minus electric charge are OH-ions contained in water and minus ions contained in resin.
Since the p layer 134 is at a lower potential than the p layer 135, the forward field plate R which is at the same potential as the p layer 134 becomes lower in potential than the n- layer 12. Consequently, the n- layer 12 under the forward field plate is apt to undergo P inversion. Further, the surface of the n- layer 12 which is exposed through the insulating film 30 also undergoes p inversion in the presence of minus electric charge, so that the p layers 134 and 135 are potentially connected together through the p inversion layer, whereby the effect of FLR is impaired and the blocking voltage decreases.
As a structure for preventing the above inconvenience, such a termination structure as shown in FIG. 6 is described in Japanese Patent Laid Open No. Sho 59-76466. By providing a reverse field plate L in each of the FLRs 131, 132, 133, 134 and 135, the formation of the p inversion layer is prevented and the blocking voltage becomes stable.
This structure will now be explained in more detail with reference to FIG. 7. In the presence of the reverse field plate L, the potential of the p layer 135 located on the high potential side is controlled by the auxiliary electrode 225 and the potential of the surface of the n- layer 12 under the reverse field plate L can be relaxed and fixed. Since the potential of the reverse field plate L becomes higher than that of the surface of the n- layer 12 which underlies the reverse field plate, there is not formed a p inversion layer, and since the p layers 134 and 135 are not at the same potential, the blocking voltage does not drop and stabilization is attained. However, when the inverter train travels near the seashore, it is effected by salt water and particularly the reverse field plate L assumes an elongated state by the plus electric charge of sodium ions, so that the electric field at the corner region of the p layer becomes strong and the blocking voltage drops. This inconvenience is caused not only by sodium ions but also by alkali metal ions contained in a module resin or alkali metal ions which are contaminated unavoidably during the fabrication of the semiconductor device and module.
On the other hand, such a structure as shown in FIG. 8, having both structures of FIGS. 5 and 7 and having both forward field plate R4 and reverse field plate L4, is conceivable. By adopting such a structure there is attained stabilization of the blocking voltage, but variation in production is conspicuous and the yield is poor. As a result of investigation of the cause made by the present inventors it turned out that the organic resin covering the insulating film 30 of the semiconductor device 1 were polarized into plus and minus in a blocking voltage test, causing disturbance of the equipotential lines 40. It has also been observed in accordance with OBIC (optical beam induced current) method for example that the occurrence of voids or cracks of resin which is introduced inevitably in the course of manufacture or the formation of substances different in dielectric constant such as foreign matters on the insulating film 30 results in distortion of the equipotential lines 40, making it impossible to obtain a desired blocking voltage stably. Such inconveniences occur in a trial test of an inverter train. Due to variations in temperature of the semiconductor devices between stations and deterioration of the package caused by changes in the environment during the four seasons, there occur cracks or a change in quality of resin, etc., with the result that the dielectric constant on the insulating film 30 changes and the blocking voltage varies.
The present invention has been accomplished in view of the above-mentioned problems and aims at realizing a planar type semiconductor device stable in blocking voltage and high in yield, as well as a power converter using the same.